Configuring a Done Bit for the HMC7-MI-O1 High Speed Counter

Solution

Tag Configuration:

In MAPware-7000 first configure HMC7-MO-01 in Slot1 and HMC7-MO-02 in Slot2 then the relevant expansion port with the HMC7-MI-01 module.  This is done from the IO Allocation –> Expansion folder of the project directory.

MAPware-7000 will automatically allocate the tags in Table 1 when the IO module is configured.

Table 1 – Tags automatically allocated when IO module is configured in port:

In addition the tags in Table 2 need to be manually configured. Tags are configured in the Tags folder of the project directory. To add a tag right click in the tag list and select add. Table 2 shows the tags configured for to enable a done bit for HSC Channel 1, to implement a done bit for HSC Channel 2 the tags will need to be duplicated with different addresses.

Table 2 – Tags manually configured to implement HSC done bit using HMC7-MI-01:

Ladder Logic Configuration:

Once the tags are created a logic block can be constructed to copy the values in the 32 – bit HSC registers to internal registers, where the individual words can be compared using ladder logic instructions.

Create a new logic block by right clicking on the Main folder and selecting New Logic Block.

In the logic block insert two rungs and add a NO contact configured to read the Enable HSC Done Bit … in each rung. Next add a Move DW instruction to transfer the values from the High Speed Counter (HSC) Register… register and the HSC Preset Register… register to the HSC Counter Local… and HSC Preset Local… registers. Configure the built in HSC tags as the Operand A (Source) of the Move DW instructions, and the Local tags as Operand B (Destination) of the instructions. The High Word and Low Word tags will automatically be aligned to the proper word in the “Local” tags.

Next create logic to compare the individual words of the counter and preset registers. The logic must be implemented as shown in Table 3.

Table 3 Truth Table for HSC Done Bit

The ladder logic segment in Figure 4 implements the logic in Table 3.

This logic rung uses two branches the first branch uses a greater than  instruction to set the HSC Done… bit if the high word of the counter register is greater than the high word of the preset register. This corresponds to the second True condition in Table 3. Configure Operand A with the HSC Counter High Word… tag. Configure Operand B with the HSC Preset High Word… tag.

The second branch uses two compare instructions in a series (AND) configuration.  the enable bit and the HSC High Word Done … bit as normally open input conditions. Then there are two compare instructions in parallel (OR) configuration.

 The first compare instruction is a Greater Than Or Equal to instruction that compares HSC Counter Low Word… (Operand A) to HSC Preset Low Word… (Operand B). 

Thus if the logic is enabled AND the high word of the counter is equal to the high word of the  preset register AND the low word of the counter register is greater than or equal to the low word of the preset register THEN the HSC Done Bit is set. This corresponds to the first TRUE output in Table 3.

The second compare instruction is a Greater Than instruction that is configured to be true if the HSC Counter High Word… (Operand A) is greater than HSC Preset High Word… (Operand B).  This corresponds to the second true entry in Table 3.    

NOTE: If the HSC counter register is incremented past 2³² the register will roll over and continue counting from zero and the done bit will be cleared.